Overview

Pick a real-world system or process and model it using Simio. Be sure it is sufficiently complex to require simulation techniques. If it is analytically tractable using any other method, then do not use simulation. Model the system as completely as necessary, conduct verification, and validation, and provide the appropriate statistics for variables of interest. Use random number streams and other methods discussed in the course. Then, model an alternative to the system / process (interventional model). Again, gather statistics for variables of interest. Compare the performance of the two models statistically.

Background

When computers were first introduced, they used vacuum tubes to execute logical commands. This technology was eventually replaced by transistors, then integrated circuits, and now by microprocessors. Manufacturing the microchips which house the microprocessors is a very complex and delicate process. Even when production of the actual microprocessor is outsourced, the process still involves several steps. Although most of these steps are automated, this process cannot be modeled accurately using standard queueing theory due to varying process times for each machine, random fluctuations in machine down time, and product inspection or testing failure. Simulation of the process allows for the examination of production times, production quantities, and server utilization which accounts for analytically intractable components.

How It’s Made - Computer Microprocessors


The importance of this simulation is directly related to the increase in demand for computing power. The increase in demand for high powered CPUs and GPUs that is manifesting itself currently is fueled by the popularity of sophisticated video games, machine learning, and cryptocurrencies. About 3,500 computers are sold every minute. Considering that the above activities are in their nascent stages, it is evident that more and more computing power will be needed as time goes on. These circumstances will the microchip manufacturing process even more relevant. As such, improvements to the system will yield dividends to companies who experience production increases that help them keep pace with future demand.

Literature Review

Microchip manufacturing is considered one of the most complex production processes in any industry ii, with over 400 steps iv from start to finish. The rate of innovation in technology (Moore’s law) gives microchip manufacturing processes a much shorter life cycle i than processes in most other industries. Innovations lead not only to product obsolescence, but also production obsolescence i with new manufacturing processes requiring huge overhauls ii. On top of this, microchip manufacturing requires huge outlays in capital to remain viable v. Microchip sales in turn, afford large price premiums ii to companies making it first to market. The potential for large profits is fleeting however. That is why microchip manufacturers look to process improvements to both decrease production costs and increase throughput iv.

The microchip manufacturing business rewards modifications that improve performance while reducing costs iv. Therefore, incorporating process improvements into a business’ overall strategy can help a company “leapfrog” its competitors iii. Exogenous performance improvements can be achieved as technologies are adopted and the company experiences positive network externalities v. One of the ways these positive externalities manifest themselves is as industry standards v that decrease the need for changes. This hints at a very important point. To “significantly reduce manufacturing cycle times, one must reduce” variability i. To find endogenous performance improvements, it is beneficial to look for improvements that reduce variability in server capacity and increase throughput which also decrease unit costs i.

i Chen, Hong, et al. “Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication.”

ii Hatch, Nile W., and David C. Mowery. “Process Innovation and Learning by Doing in Semiconductor Manufacturing.”

iii Jayanthi, Shekhar, et al. “Strategic Resource Dynamics of Manufacturing Firms.”

iv Kumar, Sameer, and Nicole Krenner. “Review of the Semiconductor Industry and Technology Roadmap.”

v Wade, James. “Dynamics of Organizational Communities and Technological Bandwagons: An Empirical Investigation of Community Evolution in the Microprocessor Market.”

Process Diagram

The process of manufacturing microchips is very a complex multi-step process. Fortunately, there are videos available online that walk one through the process of how microchips are made. In a factory where the production of the microprocessors is outsourced, the microchip production process can be simplified into three inputs (entities) entering the process at different points (sources), transitioning through multiple steps (servers), and ultimately being combined into a microchip and shipped out (sink).

Process

TThe three inputs (entities) are substrates, microprocessors, and connectors. The process undergone at the servers by the entities is best described by beginning with the Connectors. These are tin columns or balls that are first processed by a suctioning sieve which lines them up for the following step where they are placed on adhesive (columns) or flux (balls) strips then held for further processing. Concurrent with this process, a batch of Substrates are coated with flux before having Processors placed on them and then soldered on after a sample is inspected. Caps are then placed and soldered onto the Processors before the substrate with the soldered processor is pasted onto the aforementioned Connectors. At this point assembly of the microchips is complete. The chips are given a water and solvent bath, undergo quality control testing, and are then shipped. Chips that do not pass inspection or testing are rejected. In the simulation, each of the entities is assigned a corresponding source object with an interarrival time equivalent to the mode processing time of the Testing server divided by the Testing server’s capacity.

Step Object Capacity Attribute Value
1 SourceSubstrate \(\infty\) Interarrival Time 720 / 576
2 SourceProcessor \(\infty\) Interarrival Time 720 / 576
3 SourceConnector \(\infty\) Interarrival Time 720 / 576
4 FluxCoating 16 Processing Time Random.Triangular( 12, 14, 16 )
5 MountProcessor 16 Processing Time Random.Triangular( 12, 14, 16 )
6 Connector \(\infty\) Inspect Rate 0.05
7 Inspect 16 Processing Time Random.Triangular( 12, 14, 16 )
8 Connector \(\infty\) Reject Rate 0.05
9 SolderProcessor 4 Processing Time Random.Triangular( 3, 3.5, 4 )
10 MountCap 16 Processing Time Random.Triangular( 18, 20, 24 )
11 SolderingOven 72 Processing Time Random.Triangular( 54, 60, 72 )
12 LineUp 9 Processing Time Random.Triangular( 6.75, 7.5, 9 )
13 Glue 9 Processing Time Random.Triangular( 6.75, 7.5, 9 )
14 MountConnector 16 Processing Time Random.Triangular( 12, 14, 16 )
15 Cleaning 288 Processing Time Random.Triangular( 216, 240, 288 )
16 Testing 576 Processing Time Random.Triangular( 648, 720, 864 )
17 Connector \(\infty\) Reject Rate 0.05
18 Ship \(\infty\) Connected Node Testing Server
19 Reject \(\infty\) Connected Node Inspect Server, Testing Server

Capacity and processing times for each server is listed above. Capacities were gauged from a video of the manufacturing process. The quantities derived were taken, without any liberties, from what is shown in the broadcasted video. Processing times for the SolderingOven and Testing servers are given by the narrator of the video. They are assumed to have triangular distributions with minimums and maximums shifted approximately 10% away from the stated times which are being used as the modes. For all other servers, the chip capacity per minute used to estimate the mode for a triangular processing time is the chip capacity per minute of the SolderingOven server. Using the speed of the SolderingOven server, which is faster than the Testing server, allows for a bottleneck at the Testing server rather than underutilization at the SolderingOven server. This bottleneck is then used in the analysis as a point for improvement. Minimums and maximums for the other servers are also shifted approximately 10% away from the mode. Finally, reliability logic has also been added to each server to incorporate the random nature of machine failures and repair times in the model. The failure type used at each server is Processing Time Based with the default Random.Exponential(100) Uptime Between Failures and Random.Triangular(0.5,1.0,1.5) Time to Repair.

Flowcharts for Modeling

Flowchart

Verification & Validation

Verification and validation of the model is done throughout the model building process. First the model and video are gone through, step-by-step, multiple times. This step is done to uncover any errors in structural and data assumptions. The step is extremely helpful with catching data entry errors. After this, the model is run for a 30-day period to check for obvious errors. For example, this step helped identify a constraint imposed by the default settings that limits the maximum number of entities in the system to 2,500. This constraint impedes this model, as it is not applicable to this microchip manufacturing process. The next step is to examine the face validity of the model and see if the model agrees with assumptions on number of units produced and utilization. This step helps reveal design and data entry errors. This model had an error in the interarrival time that surfaced in this step. Finally, model outputs are examined to see if there are any serious departures from what would be reasonable. After running the model, the number of entities processed is as expected. It is approximately equivalent to the capacity of the bottleneck (Testing) which runs 12 hours with 576 chips, multiplied by 30 days: \(576\cdot12\cdot30=34560\). The number of rejected chips is approximately equal to 5% of the 5% of chips selected for inspection, plus 1% of the chips rejected after Testing: \(34560[0.05^2+0.01(1-0.05^2 )]=34560(0.012475)\approx431\).Utilization of the bottleneck is near 100% as expected, and all other servers are at \((60/72)(720/576)=2/3\) capacity, also as expected by design.

Model Results

In the status quo model, the bottleneck is the Testing server which has a lower chip capacity per minute, at 0.8, than all the other servers, at 1.2. An interventional model that adds capacity to the Testing server, increases the capacity of the entire manufacturing process. The status quo model has two machines that can test 288 chips at a time. Adding one machine drives total capacity up to \(288\cdot3=864\). This additional machine at the Testing server increases the chip capacity per minute of the Testing server to that of all the other servers which work at much faster speeds. Increasing the speed of the system also allows for an increase in the entity Source speeds. More raw products can be fed into to this faster system.

Simulation Model

The result of implementing the interventional model is that chip production increases. It also drives up the utilization of all the non-bottleneck servers which are constrained by the speed of the bottleneck. It is also worth noting that the system can be efficiently scaled from this point if it is scaled in proportion to capacity increases in the Testing server. This insight can help with decisions regarding the repair, replacement, and retirement of technology at each server.

Statistical Results

The statistics gathered on the status quo and interventional models are from experiments consisting of 10 runs over 30 days. The variables that differ between the two experiments are the capacity of the Testing server and the interarrival times of the three entities. The statistics of interest used to compare the two models are the number of chips shipped (Ship.InputBuffer.NumberEntered) and the utilization of each server (Server.Capacity.ScheduledUtilization).

Experiement Results

The results show that increasing the capacity of the Testing server by 50% yields a nearly equivalent increase in the number of chips shipped. The difference can be attributed chips failing inspection and testing, server downtime, server repairs, and random fluctuation. It is also evident that server underutilization has ceased. Non-bottleneck servers increased utilization around 40% and all operating at nearly 100% utilization. This is due to the 50% increase in the interarrival times of the entities. Had the Testing server capacity not increased, the system would not have been able to handle the increased inputs or production.

Property Status Quo Interventional
TestingCapacity 4184*2 4184*3
ChipsPerMin 720 / (4184*2) 720 / (4184*3)
NumShipped 31957.6 46567.6
UFluxCoating 70.0097 99.1386
UMountProcessor 69.9703 98.666
USolderProcessor 69.7904 98.3124
UMountCap 68.6492 96.6979
USolderingOven 68.5776 96.498
ULineUp 68.8743 99.0552
UGlue 68.8734 98.6208
UMountConnector 69.6427 97.6233
UCleaning 68.3068 95.7592
UTesting 97.3833 94.6355

Conclusions

The most complex part of this system was modelling the process. There were several moving parts. Three entities, three source objects, nine servers, two combiners, six weighted connectors, and two sinks. A model this complex creates several opportunities for errors and requires strong attention to detail. This attention to detail however, improves the quality of the model significantly. It is also challenging to model the scenario based from a video. The inability to see the process forced the use of assumptions in areas which had to be examined more critically than they would have had the process been personally observe red. It was surprising how it all worked out however. After it was put together using the observations from the video, everything fit together almost seamlessly. For example, the capacities of servers all had a common denominator that facilitated the application of an interventional model. It wouldn’t be surprising to find out that the video was intentionally made to capture actual capacities by someone familiar with operations management.

Takeaways

The process of manufacturing microchips is highly complex. By modelling the process, I was to learn about the production process in its entirety and each step individually. I learned about adhesives, sieves, tin connectors, solvent baths, and much more. I also learned about conducting observations for modelling and the level of attention needed to understand production processes. By simulating the process, I learned how complicated a discrete process can become when randomness is introduced. Standard queuing theory cannot adequately predict performance of a system with so many moving random parts. Especially with entities arriving at a pace that exceeds capacity. I also learned how important precise modelling is to simulation. Accurately capturing the process with a model makes simulations and simulated changes extremely reliable pieces of information. If a company were to invest enough resources into modelling and simulating a process accurately, they would benefit greatly. It is highly cost-effective to model and simulate process changes rather implementing the changes based on a theoretical analysis alone; much less no analysis at all. This benefit is compounded even further when examining multiple changes.

References

Chen, Hong, et al. “Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication.” Operations Research, vol. 36, no. 2, 1988, pp. 202-215. JSTOR, JSTOR, www.jstor.org/stable/171276.

“Computer Microprocessors.” How It’s Made: Second Season 2 Episode 14 Segment D, written by Lynn Herzeg, narrated by Brooks T. Moore, directed by Gabriel Hoss, Discovery Channel, 2002.

Discrete-Event Systems Simulation, 5th Edition (2010), by Jerry Banks, John S. Carlson, Barry L. Nelson,and David M. Nicol.

Hatch, Nile W., and David C. Mowery. “Process Innovation and Learning by Doing in Semiconductor Manufacturing.” Management Science, vol. 44, no. 11, 1998, pp. 1461-1477. JSTOR, JSTOR, www.jstor.org/stable/2634893.

Jayanthi, Shekhar, et al. “Strategic Resource Dynamics of Manufacturing Firms.” Management Science, vol. 55, no. 6, 2009, pp. 1060-1076. JSTOR, JSTOR, www.jstor.org/stable/40539281.

Kumar, Sameer, and Nicole Krenner. “Review of the Semiconductor Industry and Technology Roadmap.” Journal of Science Education and Technology, vol. 11, no. 3, 2002, pp. 229-236. JSTOR, JSTOR, www.jstor.org/stable/40186546.

Simio and Simulation: Modeling, Analysis, Applications 3d Ed. by W. David Kelton, Jeffrey S. Smith and David T. Sturrock with Simio software.

Wade, James. “Dynamics of Organizational Communities and Technological Bandwagons: An Empirical Investigation of Community Evolution in the Microprocessor Market.” Strategic Management Journal, vol. 16, 1995, pp. 111-133. JSTOR, JSTOR, www.jstor.org/stable/2486772.

http://www.worldometers.info/computers/

https://www.youtube.com/watch?v=J3oL3KfqHKI

http://www.jstor.org.remote.baruch.cuny.edu/action/showAdvancedSearch

https://steinbring.net/2011/how-many-personal-computers-are-sold-per-year/